dataHAL.science
Support
https://data.archives-ouvertes.fr/author/1402
https://data.archives-ouvertes.fr/author/1402
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Modular Performance Analysis
http://xmlns.com/foaf/0.1/topic_interest
System on Chip
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https://data.archives-ouvertes.fr/subject/info.info-mo
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System-on-a-Chip
http://xmlns.com/foaf/0.1/topic_interest
Network-on-chip
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https://data.archives-ouvertes.fr/subject/info.info-mm
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https://data.archives-ouvertes.fr/subject/info.info-lo
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Relaxed memory consistency
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Invariants
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Verification
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https://data.archives-ouvertes.fr/subject/info.info-pl
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Arrival Curve
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https://data.archives-ouvertes.fr/subject/info.info-os
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https://data.archives-ouvertes.fr/subject/info.info-pf
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HPC
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Embedded systems
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Model
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Bus
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SoC
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Atmi
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Moy
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Hardware modeling
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Lesar
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Energy
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https://data.archives-ouvertes.fr/subject/info.info-sy
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Causality
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SMT Solving
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Program verification
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https://data.archives-ouvertes.fr/subject/info.info-se
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Many-core architectures
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Tdma
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Linear Priced Timed automata
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Polyhedral mode
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Temperature
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Transaction-level modeling
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Real-Time Calculus
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Test
http://www.openarchives.org/ore/terms/isAggregatedBy
https://data.archives-ouvertes.fr/author/matthieu-moy
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Portals 4
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Scheduling
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Systèmes embarqués
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Duration
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Index Terms-response time analysis
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Front-end
http://xmlns.com/foaf/0.1/name
Matthieu Moy
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Spin
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Java
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Electrical Rule Checking
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Parallel simulation
http://www.w3.org/1999/02/22-rdf-syntax-ns#type
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TLM
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Partial order reduction
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Worst-case execution time
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Synchronous approach
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Causalité
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Abstract interpretation
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Vérification formelle
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Real-time calculus
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Education
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High-Performance Computing
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Real-time
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Algorithm optimization
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Data restructuring
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Multi-core
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SMT
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Compilation
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Formal verification
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Granularity
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SimGrid
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LusSy
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Matthieu
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Kalray
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Static analysis
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Lustre
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Virtual prototyping
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TLM 20
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Promela
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Pinapa
http://xmlns.com/foaf/0.1/mbox_sha1sum
ea8b74cad876768eb3af64751e169c97
http://www.w3.org/2002/07/owl#sameAs
0000-0002-6054-8882
http://www.w3.org/2002/07/owl#sameAs
106984993
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Simulation
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Promises
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Parallelism
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Forbidden Regions
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Dead-lock
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Interprétation abstaite
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High-Level Synthesis
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Sémantique
http://xmlns.com/foaf/0.1/topic_interest
Formal modeling
http://xmlns.com/foaf/0.1/topic_interest
SystemC
http://xmlns.com/foaf/0.1/topic_interest
JTLM
http://xmlns.com/foaf/0.1/topic_interest
Smv
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Parallel Programming
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Multibanking
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Systèmes sur puce
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Parser
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Wcet
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Review
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Interconnect
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Calcul temps-réel
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Validation
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Model-checking
http://xmlns.com/foaf/0.1/topic_interest
FPGA
http://xmlns.com/foaf/0.1/topic_interest
BXI
http://xmlns.com/foaf/0.1/topic_interest
Real-time systems
http://xmlns.com/foaf/0.1/topic_interest
DPOR
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SMT-solving
http://xmlns.com/foaf/0.1/interest
https://data.archives-ouvertes.fr/subject/info.info-ar
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Rollback
http://xmlns.com/foaf/0.1/topic_interest
Loose timing
http://xmlns.com/foaf/0.1/topic_interest
Loosely-timed
http://xmlns.com/foaf/0.1/topic_interest
Treasure Hunt
http://xmlns.com/foaf/0.1/topic_interest
SSA
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https://data.archives-ouvertes.fr/subject/info.info-cl
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Parallelization
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Transaction-Level-Modeling
http://xmlns.com/foaf/0.1/topic_interest
Power estimation
http://xmlns.com/foaf/0.1/interest
https://data.archives-ouvertes.fr/subject/info.info-cc
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Unix
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Programming Models
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MPI
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Parallélisme
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https://data.archives-ouvertes.fr/subject/info.info-fl
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https://data.archives-ouvertes.fr/subject/info.info-ds
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Coverage
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https://data.archives-ouvertes.fr/subject/info.info-es
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https://data.archives-ouvertes.fr/subject/info.info-dc
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Modélisation
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Modeling
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Exam
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Semantics
http://xmlns.com/foaf/0.1/topic_interest
Algorithms
http://xmlns.com/foaf/0.1/topic_interest
Faithfulness issues
http://xmlns.com/foaf/0.1/topic_interest
Integrated Circuits
https://aurehal.archives-ouvertes.fr/author/1402
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